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UTOPIA.I.O 4-PORT (128 X 9 X 4) MULTIPLEXER-.I.O
.eatures
x x x x
1,6%%!#
x x
x
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Four Independent Input 128 x9 FIFO Queues Nine bit wide input FIFOs Single selectable 9 or 18 bit output bus "UtopiaRx" or "UtopiaTx" Utopia compliant interface signaling options Separate clocks for input and output Selectable Automatic byte insertion for 8-bit Receive Utopia to 16bit Receive Utopia compliance Four 155Mbs ATM input channels can be consolidated into a single 622Mbs channel with no additional glue logic Maximum through put per device over 1.4Gbps
x
x
x x x x
x
In a building block configuration multiple input channels can be multiplexed onto a 32, 64 or 128 bit bus. User programmable: - byte insert/delete, UtopiaTx/UtopiaRx mode, master/slave configuration, byte swapping Selectable Round Robin Sequencer output control Data clock rates to 80 MHz; access times 8.5 ns 100-pin TQPF package Separate cell ready signals for each FIFO and cell ready composite signal End of cell transfer flag
.unctional Block Diagram
CRn
CRC ECT CSS RTS BDI
CELL SIZE/CELL READY
OE
RST
WCLK
ROUND ROBIN SEQUENCER
MSE
RRE RCLK MUX1 MUX2 LDM X 18 SWP FIFO CONTROLLER 128 BYTES FIFO
ENR a CLAVR a SOCR a Data a (0 - 8) ENR b CLAVR b SOCR b Data b (0 - 8) ENR c CLAVR c SOCR c Data c (0 - 8) ENR d CLAVR d SOCR d Data d (0 - 8)
FIFO CONTROLLER 128 BYTES FIFO
XOE ENS CLAVS SOCS
,
FIFO CONTROLLER 128 BYTES FIFO
Q0 - Q8 Q9 - Q17
FIFO CONTROLLER 128 BYTES FIFO BSS
3206 drw 01
MARCH 2001
1
(c)2001 Integrated Device Technology, Inc. DSC-3206/3
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Preliminary Commercial and Industrial Temperature Ranges
General Description
The IDT77305 UtopiaFIFO is a high-speed, low power, four to one, muxed FIFO with multiple programmable modes of operation. The IDT77305 can be used as a stand alone device or as a building block element. Within the UtopiaFIFO, the input FIFOs act as intermediate queues for the input streams to allow synchronization with a common output stream (see Functional Block Diagram). Each of the four input synchronous (clocked) FIFOs are 64 words (128 bytes) in depth. Separate input and output clocks are supported to 80 MHz. As a stand alone element four independent 9-bit input streams are concentrated onto one selectable 9 or 18-bit output bus. The Bus Size Select pin (BSS) determines the desired output bus width. In a building block configuration, multiple devices can be used to multiplex larger numbers of input streams onto output buses greater than 18 bits. The principle application is in ATM networking based systems, but can be used in any data or telecommunications application requiring the merging of independent data streams into a single output. FIFO selection for data output can be made internally via a round robin which sequentially selects one of the four FIFOs. Alternatively, external
Pin Configuration
CLAVR d ENR d RST WCLK BDI Vcc RTS BSS OE Cr0 CR1 CR2 CR3 GND CSS ECT CRC MSE RRE LDM MUX2 MUX1 RCLK SWP XOE
SOCR d Data d 8 GND Data d 7 Data d 6 Data d 5 Data d 4 Data d 3 Data d 2 Data d 1 Data d 0 ENR c CLAVR c SOCR c Data c 8 Data c 7 Data c 6 Data c 5 Data c 4 Vcc Data c 3 Data c 2 Data c 1 Data c 0 ENR b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
100 PIN TQFP PN-100
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
CLAVS ENS SOCS Vcc Q17 Q16 Q15 Q14 GND Q13 Q12 Q11 Q10 Q9 Vcc Q8 Q7 Q6 Q5 GND Q4 Q3 Q2 Q1 Q0
,
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
3206 drw 02
CLAVR b SOCR b Data b 8 Data b 7 GND Data b 6 Data b 5 Data b 4 Data b 3 Data b 2 Data b 1 Data b 0 ENR a CLAVR a SOCR a Data a 8 Data a 7 Data a 6 Data a 5 Data a 4 Data a 3 Data a 2 Data a 1 Data a 0 Vcc
2
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Commercial and Industrial Temperature Ranges
Pin Description
Name BDI BSS CLAVR a CLAVR b CLAVR c I/O I I I/O I/O I/O Description Byte Deletion/Insertion. BDI = "1" insert byte 6 or delete byte 5, BDI = "0" no change to bytes 5 or 6 (see Table 4). Bus Size Selection. BSS = "0" 18-bit output bus, BSS = "1" 9-bit output bus. Cell Available (FIFO-a)--Receive side. Rx mode: CLAVR notifies UtopiaFIFO an entire cell is available for transfer. It is an input signal. Tx mode: CLAVR notifies sending agent the UtopiaFIFO can accept an entire cell. It is an output signal. Cell Available (FIFO-b)--Receive side. Rx mode: CLAVR notifies UtopiaFIFO an entire cell is available for transfer. It is an input signal. Tx mode: CLAVR notifies sending agent the UtopiaFIFO can accept an entire cell. It is an output signal. Cell Available (FIFO-c)--Receive side. Rx mode: CLAVR notifies UtopiaFIFO an entire cell is available for transfer. It is an input signal. Tx mode: CLAVR notifies sending agent the UtopiaFIFO can accept an entire cell. It is an output signal. Cell Available (FIFO-d)--Receive side. Rx mode: CLAVR notifies UtopiaFIFO an entire cell is available for transfer. It is an input signal. Tx mode: CLAVR notifies sending agent the UtopiaFIFO can accept an entire cell. It is an output signal. Cell Available (sender side). Notifies controlling agent a cell is available. Cell Ready, FIFO-n. For OE LOW and RST HIGH, CR-n is an output (HIGH if FIFO-n has a cell available, LOW if no cell available). For RST and OE both HIGH, CR-n are tri-stated. For RST LOW and OE HIGH, CRn are inputs. See Table 1. Cell Ready Composite. For OE LOW and RST HIGH, CRC is an output (HIGH if any FIFO has cell available). For RST and OE both HIGH, CRC is tri-stated. For RST LOW AND OE HIGH, CRC is a cell size selection input [MSB]. Cell Size selection for (MSB-2). 9-bit data bus inputs for FIFO-a. 9-bit data bus inputs for FIFO-b. 9-bit data bus inputs for FIFO-c. 9-bit data bus inputs for FIFO-d. End Cell Transfer. For OE LOW and RST HIGH, ECT is an output asserted one cycle before end of current cell transfer. ECT goes LOW upon cell transfer completion. For RST and OE both HIGH, ECT is tri-stated. For RST LOW and OE HIGH, ECT is a cell size selection input [MSB-1]. Enable (FIFO-a)--Receive Side. Rx mode: ENR is an output initiating data transfer to the receiver (input) side. Tx mode: ENR is an input initiating data transfer to the receiver side. Enable (FIFO-b)--Receive Side. Rx mode: ENR is an output initiating data transfer to the receiver (input) side. Tx mode: ENR is an input initiating data transfer to the receiver side. Enable (FIFO-c)--Receive Side. Rx mode: ENR is an output initiating data transfer to the receiver (input) side. Tx mode: ENR is an input initiating data transfer to the receiver side. Enable (FIFO-d)--Receive Side. Rx mode: ENR is an output initiating data transfer to the receiver (input) side. Tx mode: ENR is an input initiating data transfer to the receiver side. Enable (sender side). Enables current word transfer. Rx mode: an input to UtopiaFIFO. Tx mode: an output to receiving system. Logic and supply ground.
3206 tbl 01
CLAVR d
I/O
CLAVS CR0 - CR3
I/O I/O
CRC CSS DATA a DATA b DATA c DATA d ECT
I/O I/O I I I I I/O
ENR a ENR b ENR c ENR d ENS
GND
I/O I/O I/O I/O I/O
____
3
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Preliminary Commercial and Industrial Temperature Ranges
Pin Description (con't.)
Name LDM MSE MUX1 MUX2 I/O I/O I I/O I/O I O I I I I I I I I O I Description Load Mux. RRE = "1" and MSE = "1": LDM is an output telling Slave to latch the Mux select address on the next clock cycle, RRE = "0" and MSE = "1": LDM is an input that latches the Mux address for the next cell transfer. Master/Slave Enable. MSE = "1" master mode, MSE = "0" slave mode. MUX1 address. With RRE = "1": MUX1 outputs FIFO address LSB: with RRE = "0": MUX1 is input address LSB of selected FIFO. MUX2 address. With RRE = "1": MUX2 outputs FIFO address MSB: with RRE = "0": MUX2 is input addre MSB of selected FIFO. Output Enable. In combination with RST, it sets CR0-3 as either output cell available signals, input cell size values or tri-state outputs (see Table 1). Data bus output. Data read clock. Round Robin Enable. RRE = "1" round robin sequencer enabled. RRE = "0" sets mux select lines and LDM as inputs to provide user control over selected FIFO. Reset. Clears all FIFO memory locations, read/write pointers, RR sequencer. Receive/Transmit mode Selection RTS = "0" Utopia Rx mode, RTS = "1" UtopiaTx mode. Start Of Cell (FIFO-a)--Receive side. Active on first byte when CLAVR and ENR are asserted. After first byte read, SOCR is ignored until full cell has been received. Start Of Cell (FIFO-b)--Receive side. Active on first byte when CLAVR and ENR are asserted. After first byte read, SOCR is ignored until full cell has been received. Start Of Cell (FIFO-c)--Receive side. Active on first byte when CLAVR and ENR are asserted. After first byte read, SOCR is ignored until full cell has been received. Start Of Cell (FIFO-d)--Receive side. Active on first byte when CLAVR and ENR are asserted. After first byte read, SOCR is ignored until full cell has been received. Start of Cell (sender side). Assertion: first word is currently on output bus. Swap Enable. Swaps high byte and low byte of current word. SWP = "0": First word is placed in lower byte (Q0-Q7) of 16-bit output (little endian), SWP = "1": first word is placed in upper byte (Q9-Q16) of 16-bit output (big endian Utopia compliant cell format). Logic and supply VCC. Data write clock. Data bus output enable.
3206 tbl 02
OE
Qn RCLK RRE
RST
RTS SOCR a SOCR b SOCR c SOCR d SOCS SWP
VCC WCLK
____
I I
XOE
4
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
Symbol VTERM TA T-Bias T-STG IOUT Terminal Voltage with respect to ground Operating Temperature Temperature under Bias Storage Temperature DC Output Current Rating Commercial -0.5 to +7.0 0 to +70 -55 to +155 -55 to +155 50 Industrial -0.5 to +7.0 -40 to +85 -55 to +155 -55 to +155 50 Unit V C C C mA
3206 tbl 03
Recommended DC Operating Conditions
Symbol VCC GND VIH VIL Commercial Supply Voltage Supply Voltage Input High Voltage Commercial Input Low Voltage Commercial Parameter Min. 4.5 0 2.0 -0.3 Typ. 5.0 0
____
Max. 5.5 0 VCC+0.3 0.8
Unit V V V V
3206 tbl 04
____
DC Electrical Characteristics
Symbol ILI ILO VOH VOL ICC1 Input Leakage Current Output Leakage Current Output Logic "1" Voltage, IOH=-4mA@2.4V Output Logic "0" Voltage IOL=+4mA@0.4V Active Power Supply Current Parameter Min. -1 -10 2.4
____
Typ.
____
Max. 1 10
____
Unit A A V V mA
3206 tbl 05
____
____
____
0.4 150
____
____
Capacitance
Symbol CIN COUT Input Capacitance Output Capacitance Parameter Conditions VIN=0V VOUT=0V Max. 10 10 Unit pF pF
3206 tbl 06
5
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Preliminary Commercial and Industrial Temperature Ranges
AC Electrical Characteristics(1)
RX Mode
(Commercial: VCC = 5V 10%, TA = 0C to +70C)
Commercial 77305L12 Symbol tCLAVS tCLAVH tENSS tENSH tPEN tPCLAV TX Mode 77305L12 Symbol tENRS tENRH tCLAVS tCLAVH tPCLAV tPENS Enable Set-up Time, ENR to WCLK Enable Hold Time, WCLK to ENR Cell Available Set-up Time, CLAVS to RCLK Cell Available Hold Time, RCLK to CLAVS WCLK to CLAVS RCLK to ENS Parameter Min. 4.5 0 5 0
____
77305L15 Min. 5 0 5 0
____
Parameter Cell Available Set-up Time, CLAVR to WCLK Cell Available Hold Time, WCLK to CLAVR Enable Set-up Time, ENS to RCLK Enable Hold Time, RCLK to ENS WCLK to ENR RCLK to CLAVS
Min. 5 0 4.5 0
____
Max.
____ ____
Max.
____ ____
Unit ns ns ns ns ns ns
3206 tbl 07
____
____
____
____
8 10
10 10
____
____
Commercial 77305L15 Min. 5 0 5 0
____
Max.
____ ____
Max.
____ ____
Unit ns ns ns ns ns ns
3206 tbl 08
____
____
____
____
10 10
10 10
____
____
(Industrial: VCC = 5V 10%, TA = -40C to +85C)
RX Mode 77305L12 Symbol tCLAVS tCLAVH tENSS tENSH tPENS tPCLAV Parameter Cell Available Set-up Time, CLAVR to WCLK Cell Available Hold Time, WCLK to CLAVR Enable Set-up Time, ENS to RCLK Enable Hold Time, RCLK to ENS WCLK to ENR RCLK to CLAVS Min. 5 0 5 0
____
Industrial 77305L15 Min. 5 0 5 0
____
Max.
____ ____
Max.
____ ____
Unit ns ns ns ns ns ns
3206 tbl 09
____
____
____
____
10 10
10 10
____
____
TX Mode 77305L12 Symbol tENRS tENRH tCLAVS tCLAVH tPCLAV tPENS Enable Set-up Time, ENR to WCLK Enable Hold Time, WCLK to ENR Cell Available Set-up Time, CLAVS to RCLK Cell Available Hold Time, RCLK to CLAVS RCLK to CLAVS RCLK to ENS Parameter Min. 4.5 0 5 0
____
Industrial 77305L15 Min. 5 0 5 0
____
Max.
____ ____
Max.
____ ____
Unit ns ns ns ns ns ns
3206 tbl 10
____
____
____
____
10 10
10 10
____
____
6
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Commercial and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load 0 to 3.0V 2ns 1.5V 1.5V See Figure 1
3240 tbl 11
AC Test Load
1.5V 50 I/O Z0 = 50
3206 drw 03
,
,
Figure 1: AC Test Load
6 5 4 tCD 3 (Typical, ns) 2 1 20 30 50 80 100 Capacitance (pF) 200
3206 drw 04
, ,
Figure 2: Lumped Capacitive Load, Typical Derating
7
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Preliminary Commercial and Industrial Temperature Ranges
AC Electrical Characteristics(1)
(Commercial: VCC = 5V 10%, TA = 0C to +70C)
Commercial Rx Mode Symbol fS tA tCLK tCLKH tCLKL tRS tRSS tRSR tPRS tSKEW1 tSKEW2 tDS tDH tSOCS tSOCH tCSS tCSH tLDMS tLDMH tMUXS tMUXH tPSOC tPCS tPLDM tPMUX tXOE tOE tXOHZ tOHZ tXOLZ tOLZ Clock Cycle Frequency Data Access Time Clock Cycle Time Clock High Time Clock Low Time Reset Pulse Width
(1)
77305L12 Parameter Min.
____
77305L15 Min.
____
Max. 80 10
____
Max. 66.7 10
____
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3206 tbl 12
2 12.5 5 5 12 12 10
____
2 15 6 6 15 15 14
____
____
____
____
____
____
____
Reset Set-up Time Reset Recovery Time Reset to Output Time Skew time between RCLK and WCLK Skew time between WCLK and RCLK Data Set-up Time, Data to WCLK Data Hold Time, WCLK to DATA SOCR Set-up Time, SOCR to WLCK SOCR Hold Time, WCLK to SOCR Cell Size Set-up Time (CRC, ECT, CSS or CRn to RST) Cell Size Hold Time (CRC, ECT, CSS, CRn to RST) Load MUX Set-up Time, LDM to RCLK Load MUX Hold Time, RCLK to LDM MUX Set-up Time, MUX to RCLK MUX Hold Time, RCLK to MUX RCLK to SOCS Cell Status Response, RCLK to CRC, ECT, CSS or CRn RCLK to LDM (as RREN=1) RCLK to MUX (as RREN-1)
(2) (2)
____
____
____
____
8
____
10
____
11 11 5 0 4.5 0 6 0 5 0 5 0
____
14 14 5 0 5 0 8 0 5 0 5 0
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
10 10 10 10 10 10 10 10
____
10 10 10 10 10 10 10 10
____
____
____
____
____
____
____
XOE to Qn Valid OE to CRC, ECT, CSS or CRn XOE to Qn in High Z(2) OE to CRC, ECT, CSS or CRn in High Z XOE to Qn in Low Z(2) OE to CRC, ECT, CSS or CRn in Low Z(2)
(2)
1 1
____
1 1
____
____
____
0 0
0 0
____
____
NOTES: 1. Pulse widths less than minimum values are not allowed. 2. Values guaranteed by design, not currently tested.
8
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics(1)
(Industrial: VCC = 5V 10%, TA = -40C to +85C)
Industrial Rx Mode Symbol fS tA tCLK tCLKH tCLKL tRS tRSS tRSR tPRS tSKEW1 tSKEW2 tDS tDH tSOCS tSOCH tCSS tCSH tLDMS tLDMH tMUXS tMUXH tPSOC tPCS tPLDM tPMUX tXOE tOE tXOHZ tOHZ tXOLZ tOLZ Clock Cycle Frequency Data Access Time Clock Cycle Time Clock High Time Clock Low Time Reset Pulse Width Reset Set-up Time Reset Recovery Time Reset to Output Time Skew time between RCLK and WCLK
(2) (1)
77305L12 Parameter Min.
____
77305L15 Min.
____
Max. 80 10
____
Max. 66.7 10
____
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3206 tbl 13
2 12.5 5 5 12 12 10
____
2 15 6 6 15 15 14
____
____ ____
____ ____
____
____
____
____
____
____
10
____
10
____
11 11 5 0 5 0 6 0 5 0 5 0
____
14 14 5 0 5 0 8 0 5 0 5 0
____
Skew time between WCLK and RCLK(2) Data Set-up Time, Data to WCLK Data Hold Time, WCLK to DATA SOCR Set-up Time, SOCR to WLCK SOCR Hold Time, WCLK to SOCR Cell Size Set-up Time (CRC, ECT, CSS or CRn to RST) Cell Size Hold Time (CRC, ECT, CSS, CRn to RST) Load MUX Set-up Time, LDM to RCLK Load MUX Hold Time, RCLK to LDM MUX Set-up Time, MUX to RCLK MUX Hold Time, RCLK to MUX RCLK to SOCS Cell Status Response, RCLK to CRC, ECT, CSS or CRn RCLK to LDM (as RREN=1) RCLK to MUX (as RREN=1)
____ ____
____ ____
____
____
____
____
____ ____
____ ____
____
____
____
____
____ ____
____ ____
____
____
10 10 10 10 10 10 10 10
____
10 10 10 10 10 10 10 10
____
____ ____
____ ____
____
____
XOE to Qn Valid OE to CRC, ECT, CSS or CRn XOE to Qn in High Z
(2)
1 1
____
1 1
____
OE to CRC, ECT, CSS or CRn in High Z(2) XOE to Qn in Low Z
(2)
____
____
0 0
0 0
OE to CRC, ECT, CSS or CRn in Low Z(2)
____
____
NOTES: 1. Pulse widths less than minimum values are not allowed. 2. Values guaranteed by design, not currently tested.
9
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Preliminary Commercial and Industrial Temperature Ranges
mux select lines provide user control of FIFO selection.
.unctional Description
SINGLE DEVICE OPERATION
The two programmable interface signaling modes of operation are Utopia Receive (UtopiaRx) and Utopia transmit (UtopiaTx). Both modes can concentrate four nine-bit channels (up to 720 Mbs) to one 18-bit output channel (up to 1.44 Gbs). In a building block implementation, multiple streams over 10 Gbs (with 32, 64, or 128 bit buses) can be obtained. Mode one, UtopiaRx, follows UtopiaRx protocols; and Mode two, UtopiaTx, follows UtopiaTx protocols. The Receive/Transmit Select (RTS) pin sets the UtopiaFIFO into the desired mode. The difference between these modes relates to the Utopia specification for signal handshaking. In UtopiaRx mode, the device receiving data controls the data flow through ENR (or ENS on the output side). In UtopiaTx mode, the device sending data controls the data flow through ENR (or ENS on the output side). This is described in the Utopia ATM-PHY Level2 version 1 Document. In either mode, data is transferred in "cells". ATM cell size is 53 bytes. However, for applications other than ATM the cell size can be programmed through the cell size register. Programming this register allows cell sizes from 8 bytes to 128 bytes. With RST and OE both HIGH, CR(0-3), CSS, ECT and CRC are cell size inputs. The default cell size of 53 bytes is selected when both RST and OE are LOW. In either case the values are latched on the rising edge of RST. To load a specific cell size value from 8 bytes to 128 bytes use CR(0-3), CSS, ECT and CRC as inputs with RST and OE both HIGH. The bit order is CR0, CR1, CR2, CR3, CSS, ECT, CRC, with CR0 being LSB and CRC being MSB. Set all input pins LOW to program a cell size of 128 bytes. See Table 1 for cell size programming truth table. Control signals for the input data (receive) side consists of CLAVR, ENR and SOCR (see Table 2a). Prior to cell transfer, the controlling agent (data source for transmit mode, data destination for receive mode) is notified a cell transfer can take place through the assertion of the CLAVR signal. Each data transfer of a cell is completed by assertion of ENR. The ENR signal is supplied by the controlling agent. During the first data byte transfer, the data source asserts SOCR to mark the beginning of the cell. Data transfer continues until the cell is completed. When the cell size is reached, further writes are blocked until new CLAVR and SOCR signals are received.
OE
1 0 1 0
RST
0 0 1 1
FUNCTION CR(0-3), CSS, ECT, CRC are cell size inputs sets default cell size of 53 bytes CR(0-3), CSS ECT, CRC are tristated CR(0-3), CSS, ECT, CRC are outputs CR(0-3) = "0" then no cell in FIFO = "1" then cell in FIFO CSS = no function: don't care ECT asserts one cycle before the end of a cell transfer CRC = "0" then no FIFO(s) has a cell CRC = "1" then at least one FIFO has cell
3206 tbl 14
TABLE 1: Truth table for cell size programming
Note values are loaded on the rising edge of RST
the same description as shown for a device in a master setting--the MSE signal is set HIGH (slave operation is described later in building block mode section). In UtopiaTx mode, the CLAVS is an input to the UtopiaFIFO signaling a complete cell can be transferred. As the controlling agent, the UtopiaFIFO asserts an output signal, ENS to transfer data on the same rising clock edge (see Figure 6).
ADDITIONAL CONTROL SIGNALS--RX AND TX MODES
Three additional control signals provide added device functionality. The global reset (RST) pin clears all register values. The byte swapping (SWP) pin provides the ability to swap byte positions on the output. SWP is a dynamic signal--once this signal is changed, output high and low bytes are swapped on the next clock cycle. If SWP is high the first byte of data is put in the upper byte of output bus, and if low the first byte is placed in the lower byte. SWP high will make the output bus Utopia compliant. The function is disabled when output bus size is set to 9-bits. The Byte Delete/ Insert (BDI) pin enables byte delete/insert to comply with ATM bus matching. The input bus is Utopia compliant 9-bit bus with the output an 18bit bus. Data is transferred to each FIFO in 53 byte cells. The Utopia spec defines 53 bytes per cell for 8-bit transfer and 54 bytes per cell for 16 bit transfer. Compatibility with 53 byte ATM cell formatting during bus matching is maintained. With the BDI selected, depending on the byte size and interface signaling mode, the UtopiaFIFO will automatically insert and/or delete dummy or header bytes according to Table 4; thus maintaining data integrity and Utopia specification compatibility. With BDI asserted HIGH, cell size is limited to 126 bytes. When output bus size is set to 9-bits, BDI must be deasserted LOW. The round robin sequencer sequentially selects one of four FIFOs to output data. The sequencer is enabled by asserting the Round Robin Enable (RRE) HIGH. The sequencer will poll each FIFO in turn to determine which has data to send and selects the appropriate FIFO.
RXMODE
In UtopiaRx mode (see Figure 2a), ENR is an output to the sending device and assertion of ENR results in data writes to the UtopiaFIFO in a pipelined fashion. Once enabled, data is written on the following rising clock edge. CLAVR controls data from the sender side. While this signal remains HIGH, data is valid. If CLAVR goes LOW, data continues to be valid after cell transfer is started. After cell transfer begins, if ENR is deasserted, data writes halt until subsequent assertions (see Figures 3). The I/O status of the output pins are listed in Table 3 for both UtopiaRx and UtopiaTx modes in either Master or Slave configuration. As a standalone device, the UtopiaFIFO has The I/O status of the output pins are listed in Table 3 for both UtopiaRx and UtopiaTx modes in either Master or Slave configuration. As a stand-alone device, the UtopiaFIFO has
10
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Commercial and Industrial Temperature Ranges
tRS
RST (I)
tPRS CLAVR (A..D) (O)
tRSS
tRSR
ENR (A..D) (I)
tPRS
ENS (O)
tPRS SOCS (O)
tPRS Q0NQ17 (O)
tPRS LDM (O)
tRSS LDM (I)
tRSR
tCSS
tCSH
OE (I)
tOHZ CR0-CR3, CRC, ECT, (I/O) CSS tCSS Input tCSH tOE Output
tOLZ
3206 drw 05
Figure 1a. Transmit Mode Reset Timing
11
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Preliminary Commercial and Industrial Temperature Ranges
tRS
RST (I)
tPCLAV CLAVR (A..D) (I)
tPRS
ENR (A..D) (O)
tPRS CLAVS (O)
tRSS
tRSR
ENS
(I)
tPRS SOCS (O)
tPRS Q0NQ17 (O)
tPRS LDM (O)
tRSS LDM (I)
tRSR
tCSS
tCSH
OE
(I) tOHZ tCSS tCSH Input tOE Output
CR0-CR3, CRC, ECT, (I/O) CSS
tOLZ
3206 drw 06
Figure 1b. Receive Mode Reset Timing
12
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Commercial and Industrial Temperature Ranges
The selection process begins one cycle prior to the completion of the current FIFOs cell transfer (as defined by the Cell Size Register). On one cycle, the UtopiaFIFO determines if a FIFO has a cell and its identity. If a cell is ready, the counter will hold the value and present it to the output of the mux select lines prior to the last word transfer of the current cell and assert the output CLAVS signal. See Figure 7 for round robin state machine. If the RRE signal is deasserted LOW, the mux select lines and LDM become inputs defining which FIFO will transfer data. Interrogation of the select signals will take place at the beginning of each clock cycle. Four cell ready pins (CR0-3) are provided so it can be determined if the port being
polled has a cell ready to transfer. With OE set LOW, CR0-3 signals indicate cell available for the four FIFOs. If a particular FIFO has a complete cell ready for output, the appropriate CR pin is asserted HIGH. All four FIFOs cell ready signals are independent of each other. CR-0, 1, 2, 3, signal cell available status for FIFO-A, B, C, D respectfully. The Cell Ready Composite (CRC) signal is a composite of all CR-n signals. If any of the FIFOs have a cell available, CRC is asserted HIGH. CRC and CR(0-3) de-assert LOW on the last byte of the current cell transfer, if there is not another complete cell to transfer. Once it has been determined that a particular FIFO has a cell to transfer the Load Mux (LDM) is asserted HIGH while that address is on
TABLE 2: Pin I/O status for Receiver and Sender Signals for Rx and Tx Modes
Receiver (Input) I/O RX CLAVR I O I I I TX O I I I I
3206 tbl 15
Receiver (Input) I/O RX CLAVR O I O O I TX I O O O I
3206 tbl 16
ENR
SOCR Data Clock
ENR
SOCR Data Clock
Rx Mode CLAVR CLAVS CLAVR
Tx Mode CLAVS
DATA
Utopia FIFO
DATA
DATA
Tx Mode Utopia FIFO
DATA
SOCR
SOCS
SOCR
SOCS
ENR
2a
ENS
ENR
2b
ENS
3206 drw 07
Figure 2. Signal and Data I/O Directions for Rx, Tx Modes.
13
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Preliminary Commercial and Industrial Temperature Ranges
the Mux1 and Mux 2 lines. This will latch the address. There must be a cell to transfer in the selected FIFO once LDM is asserted, as a new FIFO port address cannot be selected until a cell is read from the currently selected FIFO port. LDM is an input when RRE is LOW (disabled), regardless of the condition of MSE. The End of Cell Transfer (ECT) flag asserts HIGH with SOCS on the first word of the cell. ECT will de-assert LOW on the fourth to last word of the cell.
Building Block Implementation
Combining more than four data flows and/or using larger bus widths is accomplished by using the device as a building block. Multiple UtopiaFIFOs are interconnected to supply the desired bus widths and streams to be merged. Widths up to 128 bits and 32 channels are possible. Figures 8 and 9 show the control signals between Master and Slave devices and the downstream "target system" for 4 independent 9-bit channels merging to one 36-bit output bus. The Slave UtopiaFIFO output pin status is shown in Table 3. In this setup, the RRE must be disabled, and all output side control lines are inputs or not connected. As shown in Figure 8, in UtopiaRx mode, the "target" device receiving data sends the ENS signals to the Master and Slave. Output data from each UtopiaFIFO is available on the output bus on the following rising clock edge. The SOCS signal originates from the Master to alert the receiving device that respective bytes start a new cell for both UtopiaFIFOs. The MUX lines are inputs from the Master. The Master's
CLAVS notifies the receiving device that both Master and Slave UtopiaFIFOs have cells available for transfer. In UtopiaTx mode (see Figure 9), the ENS originates from the Master and is an input to the receiving device. On each assertion of ENS, data from both UtopiaFIFOs is presented to the respective output buses on the same clock cycle. The SOCS signal originates from the Master to alert the receiving device that byte starts a new cell for both UtopiaFIFOs. The receiving device sends a CLAVS to the Master and Slave to signal it can accept a new cell from both Master and Slave devices. An example of a sixteen (9-bit) channel to one (36-bit) output channel is shown in Figure 10a. Here, the first rank of UtopiaFIFOs are connected with their output low bytes each connected to 2nd rank UtopiaFIFO-5 and all output high bytes connected as inputs to 2nd rank UtopiaFIFO-6. This allows 16 (155 Mbs) channels to be multiplexed onto one 36-bit output bus (2.4Gbs). Figure 11 shows sixteen 9-bit channels multiplexed onto one 18-bit output channel.
BUILDING BLOCK MODE: 16 CHANNELS TO ONE 36-BIT OUTPUT CHANNEL FOR RX SIGNALS
The target system ENS signal in an Rx protocol feeds into all UtopiaFIFOs ENS inputs within Rank 2 (as shown in Figure 10b). As a result, a deasserted ENS will prevent data transfer from rank 2 to the target system. Data can only transfer in a pipelined fashion when ENS is active.
TABLE 3: Output Side of Utopia.I.O
RR Status Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Master/Slave Status Master Master Master Master Slave Slave Slave Slave Master Master Master Master Slave Slave Slave Slave Pin Name Rx Mode I/O I-case B O-case B O-case B O-case B (not allowed) (not allowed) (not allowed) (not allowed) I O O I I-case D N/C-case D N/C-case D I-case D Tx Mode I/O O-case A I-case A O-case A O-case A (not allowed) (not allowed) (not allowed) (not allowed) O I O I N/C-case C I-case C N/C-case C I-case C
3206 tbl 17
ENS
CLAVS SOCS MUX
ENS
CLAVS SOCS MUX
ENS
CLAVS SOCS MUX
ENS
CLAVS SOCS MUX
14
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Commercial and Industrial Temperature Ranges
All first Rank UtopiaFIFOs are set as Masters with the second Rank having one Master and one Slave. The master/slave control signaling for the Rx mode is shown in Figure 10c. After the Mux select signals are set, they are loaded into the Slave from the Master on the LDM rising clock edge. Once the mux signals are loaded either externally or internally via Round Robin Sequencer, the CLAVS from either Rank 1 or Rank 2 devices goes HIGH once a cell is available. The receiving system must issue an active ENS signal once it can accept a cell. When the CLAVS from Rank 2 and the receiving ENS signal are both asserted, data will be put on the output bus (from both the Master and Slave devices) on the clock cycle following assertion of ENS. In this setup, ENS from the receiving system MUST be asserted when it can accept data regardless of the CLAVS signals (the target must not monitor CLAVS before asserting ENS). As shown in Figure 10c, if ENS is low prior to CLAVS assertion, then once CLAVS is asserted, data is placed on the 36-bit bus on the same cycle. If CLAVS is asserted before ENS, then once ENS is active, data is placed on the output bus on the next cycle. With the first output word, SOCS is asserted for one cycle. Data is synchronized between the Master and Slave internally. The Master will assert LDM and Mux1 and Mux2 to the Slave two cycles prior to data transfer to allow the Slave time to transfer data through internal registers; it places data on the output bus two cycles later. The receiving system can throttle data via the ENS signal.
case of 16 channels to one 36-bit output channel, the second rank of UtopiaFIFOs controls data flow to the downstream system via the ENS signals. The data flow from rank 1 to rank 2 is controlled by rank 1. Data flow into rank 1 is controlled by the upstream system as described earlier for a single device mode. This signal control is shown in Figure 10d. Initially, the Mux select lines for the Master (either via round robin or through external selection) are selected and then loaded into the Slave on the rising edge of LDM. Once both ENS from the Master and CLAVS from the receiver are asserted, valid data is placed on the bus in 2 cycles. Data from the Slave is placed on the bus two cycles after the LDM signal is received and when CLAVS is asserted. For the first data word, SOCS is asserted. Until an entire cell is transferred, CLAVS can be HIGH or LOW. The transmitting device starts to monitor the CLAVS signal four cycles prior to a completed cell transfer. If the receiving device (either downstream system or rank 1 or rank 2 devices) cannot accept another cell transfer, it must deassert the CLAVS signal no later than this cycle. The Utopia FIFO devices will determine if a second cell can be sent on the second cycle prior to last word transfer.
Cell Length Error Recovery
After the start of cell signal (SOCR) is received, future SOCR assertions prior to the end of current cell transfers are ignored. A counter keeps track of byte transfer. If a "short cell" occurs (where a SOCR signal is received prior to the end of cell transfer), the SOCR is ignored and the data from the next incoming cell is loaded into the existing "short cell" until it is filled to normal cell size. Any additional bytes from the incoming cell are ignored. The short cell and next subsequent cell contents are bad data. Recovery occurs on the third incoming cell. If a "long cell" occurs (where the number of bytes exceeds the defined cell size and no new SOCR signal received indicating a new cell), the extra bytes are ignored by the UtopiaFIFO. The FIFO receiving the long cell will wait for a new SOCR (and assertion of ENR and CLAVR) before continuing data transfer.
BUILDING BLOCK MODE: 16 CHANNELS TO ONE 36-BIT OUTPUT CHANNEL FOR TX SIGNALS
In transmit Utopia mode, the data transmitter controls data flow. For the
TABLE 4: Truth Table Byte Insertion/Deletion Locations
Mode 1 2 3 4 5 6 Tx/Rx Mode Don't Care Don't Care Tx Rx Tx Rx Byte Size Even Odd Even Even Odd Odd Ins/Del Selected 0 0 1 1 1 1 No added or deleted bytes Byte insert to last high byte position Delete byte 5, insert byte to last high byte position Insert byte 6, insert byte to last high byte position Delete byte 5 Insert byte 6
3206 tbl 18
Result
15
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
tCLK
Preliminary Commercial and Industrial Temperature Ranges
WCLK (I)
tCLAVS
tCLKH
tCLKL tCLAVH
CLAVR (I) ENR (O)
tSOCS tSOCH
SOCR (I)
tDS tDH Data Valid Data Valid Data Valid
DATA (I)
Data Valid
Figure 3. UtopiaFIFO Rx Mode Input Waveforms
3206 drw 08
tCLK
RCLK (I)
tCLKH tPCLAV tCLKL
CLAVS (O)
tENSS
tENSH
ENS (I)
tPSOC tPSOC
SOCS (O)
tA tA
Q 0 - 17 (O)
tMUXS tMUXH
word 1
word 2 word (n-2)
word (n-1)
word n
word 1
word 2 FIFO Y or (X+1)
FIFO X tMUXS FIFO Y
tMUXH
MUXn (I)
FIFO X tPMUX tPMUX FIFO X tLDMS tLDMH FIFO (X+1)
(1)
MUXn (O)
(2)
LDM (I)
tPLDM tPLDM
(3)
LDM (O)
3206 drw 09
(4)
Figure 4a. UtopiaFIFO Rx Mode Output Waveforms (CLAVS Stays High)
NOTES: 1. RR = LOW 2. RR = HIGH 3. MSE = LOW 4. MSE = HIGH 5. n = cell size (in words)
16
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Commercial and Industrial Temperature Ranges
RCLK (I)
tPCLAV tPCLAV
CLAVS (O)
tENSS
ENS (I)
tPSOC tPSOC
SOCS (O)
tA tA
word 1 word 2
word 3 word (n-2) word (n-1)
tA
word n word 1
Q 0 - 17 (O)
FIFO X tPMUX
FIFO Y or (X+1)
MUXn (O)
(1)
(2)
FIFO X
FIFO (X+1)
tMUXS
tMUXH
FIFO Y
MUXn (I) LDM (O)
(4)
FIFO X
tPLDM
tPLDM
tLDMS
tLDMH
LDM
(3)
(I)
3206 drw 10
NOTES: 1. RR = LOW 2. RR = HIGH 3. MSE = LOW 4. MSE = HIGH 5. n = cell size (in words)
Figure 4b. UtopiaFIFO Rx Mode Output Waveforms (Data Validity for Variable CLAVS)
tCLK
WCLK (I) CLAVR (O)
tPCLAV tCLKH tCLKL
tENRH
tENRH tENRS
E NR (I)
tSOCS
tENRS
tSOCH
SOCR (I)
tDS tDH tDS tDH
DATA (I)
Data Valid
Data Valid
3206 drw 11
Figure 5a. UtopiaFIFO Tx Mode Input Waveforms
17
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Preliminary Commercial and Industrial Temperature Ranges
WCLK (I)
tPCLAV tPCLAV
CLAVR (O)
tENRS tENRH tSOCS tENRS tENRH
ENR (I)
tSOCH
SOCR (I)
tDS tDH LB-5 LB-4 LB-3 word x tDS LB-2 tDH LB-1 LB Byte 1 Byte 2 word (x + 1)
3206 drw 12
tDS Byte 3
Data (I)
LB-6
Figure 5b. UtopiaFIFO Tx Mode Input Waveforms (Continuous Cell Transfers)
RCLK (I)
tCLAVH tCLAVS tPENS tCLAVH
CLAVS (I)
ENS (O)
tPSOC tPSOC
SOCS (O)
tA tA
word 1 word 2
word 3 word (n-2) word (n-1)
tA
word n word 1
Q 0 - 17 (O)
(1)
FIFO X
tMUXS
FIFO Y
tMUXH
FIFO Y or (X+1)
MUXn (I)
FIFO X
tPMUX
MUXn (O)
(2)
FIFO X
FIFO (X+1)
tLDMS
tLDMH
LDM
(3)
(I)
tPLDM tPLDM
LDM
(4)
(O)
3206 drw 13
Figure 6. UtopiaFIFO Tx Mode Output Waveforms
NOTES: 1. RR = LOW 2. RR = HIGH 3. MSE = LOW 4. MSE = HIGH 5. n = cell size (in words)
18
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Commercial and Industrial Temperature Ranges
XXXX
100 00X1 XX1X
101 XXXX
0010 001
000 0000
0001
0000
XX10
X1XX
0XX1
X10X X10X XXX1
10XX 0X10
0000 100X 011 0000 1000 XXXX 111 1XXX X100 XXXX 0100 110 010
NO TE :
L D M M u x2 M u x1 C L A V [3 :0 ] In itial C ond ition S e t th e M u x 2 , M u x 1 = 1 1 R e s e t th e L D M = 0 R e s e t C L A V [3 :0 ] = 0 0 0 0
3206 drw 14
Figure 7. Round Robin State Machine
19
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Preliminary Commercial and Industrial Temperature Ranges
MRT MASTER (B)
ENS CLAVS
LDM SOCS MUX TARGET
ENS
CLAVS
MRT SLAVE (D)
SOCS
ENS CLAVS SOCS
LDM MUX
OPEN OPEN
3206 drw 15
Figure 8. UtopiaRx Output Signaling: Master/Slave Building-Block Configuration for 4 Channel Input to 1 36-bit Output
Vcc
MRT MASTER (B)
ENS CLAVS
SOCS LDM MUX
ENS
CLAVS
TARGET
MRT SLAVE (D)
SOCS OPEN OPEN
3206 drw 16
ENS CLAVS
SOCS LDM MUX
Figure 9. UtopiaTx Output Signaling: Master/Slave Building-Block Configuration for 4 Channel Input to 1 36-bit Output
NOTES: M -- Master/Slave Enable (MSE) pin R -- Round Robin Enable (RRE) pin T -- Rx/Tx Select (CRTS) pin
20
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Commercial and Industrial Temperature Ranges
9 36
9 L UtopiaFIFO #1 H 9
UtopiaFIFO #5
18
UtopiaFIFO #2
L H
36
L UtopiaFIFO #3 H
UtopiaFIFO #6
18
UtopiaFIFO #4
L H
Rank 1
Rank 2
3206 drw 17
Figure 10a. 16 9-bit Channels to One 36-bit Channel Implementation
21
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
delete
Preliminary Commercial and Industrial Temperature Ranges
RANK 1 UtopiaFIFO #1
CLAVS-R1 VCC CLAVS M RANK 1 UtopiaFIFO #2 SOCS R T
ENS
QL QH 9
9
MASTER Rank 2
ENR
CLAVR DATA L SOCR LDM M1
CLAVS
CLAVS-R2
ENS
Qout M2 36 18
ENS
RANK 1 UtopiaFIFO #3
OPEN LDM M1 M2 CLAVS CLAVS-R2
ENR
CLAVR DATA H SOCR
ENS
Qout 18
SLAVE Rank 2 RANK 1 UtopiaFIFO #4 M R T
3206 drw 18
Figure 10b. Rx Mode -- Data/Control Signaling
NOTE: 1. Rank 1 devices 1, 3, and 4 connect the same as device 2. 2. Control Signals shown pertain to connections from Rank 1--Utopia #2 to Rank 2 Master, Slave devices. Each Rank 2 device has additional identical connections to both Master/Slave devices from each Rank 1 device.
22
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
ENS (I)
ENR (O )
ENS (I)
23
Commercial and Industrial Temperature Ranges
Figure 10c. Rx Mode--Rank 1 to Rank 2 and Rank 2 to Downstream System Output Timing
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Preliminary Commercial and Industrial Temperature Ranges
RANK 1 UtopiaFIFO #1
VCC CLAVS M RANK 1 UtopiaFIFO #2 SOCS R T
ENS
QL QH
9
MASTER Rank 2
ENR
CLAVR DATA L SOCR LDM M1
CLAVS
ENS
18 Qout M2 36
RANK 1 UtopiaFIFO #3
LDM
M1
M2 CLAVS
ENR
OPEN CLAVR 9 DATA H SOCR SLAVE Rank 2 RANK 1 UtopiaFIFO #4 M R
ENS
Qout 18
OPEN
T
VCC
3206 drw 20
Figure 10d. Tx Mode -- Data/Control Signaling
NOTE: 1. Rank 1 devices 1, 3, and 4 connect the same as device 2. 2. Control Signals shown pertain to connections from Rank 1--Utopia #2 to Rank 2 Master, Slave devices. Each Rank 2 device has additional identical connections to both Master/Slave devices from each Rank 1 device.
24
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Commercial and Industrial Temperature Ranges
RANK 2
RCLK (I)
ENS (O)
CLAVS (I) SOCS (O) Q0-Q17 (O) M1, M2 (I,O) BI B2 LB2 LB1 LB B1 LB2 LB1 LB
LDM (I, O)
3206 drw 21
Figure 10e. Tx Mode--Output Timing
RANK 2
RCLK (I)
ENS (O)
CLAVS (I) SOCS (O) Q0-Q17 (O) M1, M2 (I,O) BI B2 LB2 LB1 LB B1 B2 B3
LDM (I, O)
3206 drw 22
Figure 10e. Tx Mode--Output Timing (cont.)
NOTE: 1. B1 - Byte One of cell LB - Last Byte of cell LB1 - Second to Last Byte of cell
25
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Preliminary Commercial and Industrial Temperature Ranges
L UtopiaFIFO H 1 BSS 9
L UtopiaFIFO H 2 BSS
9
9
UtopiaFIFO 5
18
L UtopiaFIFO H 3 BSS 9
L UtopiaFIFO H 4 BSS
Figure 11. 16 9-bit Channels to One 18-bit Channel Implementation
3206 drw 23
26
IDT77305 UtopiaFIFOTM 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Commercial and Industrial Temperature Ranges
Ordering Information
IDT NNNNN Device Type A Power NNN Speed A Package A Process/ Temp. Range Blank I PF Commercial Industrial 100-Pin TQFP
12 15 L 77305
Speed Grade
4 to 1 UtopiaFIFO 4-Port (128 x 9 x 4) Multipleing FIFO
3206 drw 24
,
Datasheet Document History
12/1/95: 1/15/95: 8/14/95: 12/3/96: 1/12/98: 3/14/00: 3/26/01: Initial Draft Corrected Typographical Errors Added AC specs and correct diagrams and upgraded to "PRELIMINARY" Changed the definition of LDM to reflect correct funtionallity Corrected multiple errors in text and timing diagrams Changed datasheet design format Changed Preliminary to Final. In AC Characteristics Table, changed maximum from 8 to 10 for following pins: tPCLAV, tPENS, tPSOC, tPLDM, tPMUX, tXOE, tOE, tXOHZ, tOHZ, tPRS, and tA. In same table, changed minimum from 4.5 to 5 for pins tMUXS, tLDMS, tSOCS, tDS, tCLAVS, and tENSS.
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27

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